/*
 * File      : dm368.h
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006, RT-Thread Develop Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://openlab.rt-thread.com/license/LICENSE
 *
 * Change Logs:
 * Date                Author       Notes
 * 2011-03-25     lgnq           first version
 */

#ifndef __DM368_H__
#define __DM368_H__

#include <rtthread.h>

/*
 * Peripheral identifiers/interrupts.
 */
#define IRQ_VDINT0       0
#define IRQ_VDINT1       1
#define IRQ_VDINT2       2
#define IRQ_HISTINT      3
#define IRQ_H3AINT       4
#define IRQ_PRVUINT      5
#define IRQ_RSZINT       6
#define IRQ_VFOCINT      7
#define IRQ_VENCINT      8
#define IRQ_ASQINT       9
#define IRQ_IMXINT       10
#define IRQ_VLCDINT      11
#define IRQ_USBINT       12
#define IRQ_EMACINT      13
    
#define IRQ_CCINT0       16
#define IRQ_CCERRINT     17
#define IRQ_TCERRINT0    18
#define IRQ_TCERRINT     19
#define IRQ_PSCIN        20
    
#define IRQ_IDE          22
#define IRQ_HPIINT       23
#define IRQ_MBXINT       24
#define IRQ_MBRINT       25
#define IRQ_MMCINT       26
#define IRQ_SDIOINT      27
#define IRQ_MSINT        28
#define IRQ_DDRINT       29
#define IRQ_AEMIFINT     30
#define IRQ_VLQINT       31
#define IRQ_TINT0_TINT12 32
#define IRQ_TINT0_TINT34 33
#define IRQ_TINT1_TINT12 34
#define IRQ_TINT1_TINT34 35
#define IRQ_PWMINT0      36
#define IRQ_PWMINT1      37
#define IRQ_PWMINT2      38
#define IRQ_I2C          39
#define IRQ_UARTINT0     40
#define IRQ_UARTINT1     41
#define IRQ_UARTINT2     42
#define IRQ_SPINT0       43
#define IRQ_SPINT1       44
    
#define IRQ_DSP2ARM0     46
#define IRQ_DSP2ARM1     47
#define IRQ_GPIO0        48
#define IRQ_GPIO1        49
#define IRQ_GPIO2        50
#define IRQ_GPIO3        51
#define IRQ_GPIO4        52
#define IRQ_GPIO5        53
#define IRQ_GPIO6        54
#define IRQ_GPIO7        55
#define IRQ_GPIOBNK0     56
#define IRQ_GPIOBNK1     57
#define IRQ_GPIOBNK2     58
#define IRQ_GPIOBNK3     59
#define IRQ_GPIOBNK4     60
#define IRQ_COMMTX       61
#define IRQ_COMMRX       62
#define IRQ_EMUINT       63
    
#define DAVINCI_N_AINTC_IRQ    64
    
#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
    
/* DaVinci DM6467-specific Interrupts */
#define IRQ_DM646X_VP_VERTINT0  0
#define IRQ_DM646X_VP_VERTINT1  1
#define IRQ_DM646X_VP_VERTINT2  2
#define IRQ_DM646X_VP_VERTINT3  3
#define IRQ_DM646X_VP_ERRINT    4
#define IRQ_DM646X_RESERVED_1   5
#define IRQ_DM646X_RESERVED_2   6
#define IRQ_DM646X_WDINT        7
#define IRQ_DM646X_CRGENINT0    8
#define IRQ_DM646X_CRGENINT1    9
#define IRQ_DM646X_TSIFINT0     10
#define IRQ_DM646X_TSIFINT1     11
#define IRQ_DM646X_VDCEINT      12
#define IRQ_DM646X_USBINT       13
#define IRQ_DM646X_USBDMAINT    14
#define IRQ_DM646X_PCIINT       15
#define IRQ_DM646X_TCERRINT2    20
#define IRQ_DM646X_TCERRINT3    21
#define IRQ_DM646X_IDE          22
#define IRQ_DM646X_HPIINT       23
#define IRQ_DM646X_EMACRXTHINT  24
#define IRQ_DM646X_EMACRXINT    25
#define IRQ_DM646X_EMACTXINT    26
#define IRQ_DM646X_EMACMISCINT  27
#define IRQ_DM646X_MCASP0TXINT  28
#define IRQ_DM646X_MCASP0RXINT  29
#define IRQ_DM646X_RESERVED_3   31
#define IRQ_DM646X_MCASP1TXINT  32
#define IRQ_DM646X_VLQINT       38
#define IRQ_DM646X_I2CINT       39 //fify
#define IRQ_DM646X_UARTINT2     42
#define IRQ_DM646X_SPINT0       43
#define IRQ_DM646X_SPINT1       44
#define IRQ_DM646X_DSP2ARMINT   45
#define IRQ_DM646X_RESERVED_4   46
#define IRQ_DM646X_PSCINT       47
#define IRQ_DM646X_GPIO0        48
#define IRQ_DM646X_GPIO1        49
#define IRQ_DM646X_GPIO2        50
#define IRQ_DM646X_GPIO3        51
#define IRQ_DM646X_GPIO4        52
#define IRQ_DM646X_GPIO5        53
#define IRQ_DM646X_GPIO6        54
#define IRQ_DM646X_GPIO7        55
#define IRQ_DM646X_GPIOBNK0     56
#define IRQ_DM646X_GPIOBNK1     57
#define IRQ_DM646X_GPIOBNK2     58
#define IRQ_DM646X_DDRINT       59
#define IRQ_DM646X_AEMIFINT     60    
    
/* DaVinci DM365-specific Interrupts */
#define IRQ_DM365_INSFINT    7
#define IRQ_DM365_IMXINT1    8
#define IRQ_DM365_IMXINT0    10
#define IRQ_DM365_KLD_ARMINT    10
#define IRQ_DM365_IMCOPINT    11
#define IRQ_DM365_RTOINT    13
#define IRQ_DM365_TINT5        14
#define IRQ_DM365_TINT6        15
#define IRQ_DM365_SPINT2_1    21
#define IRQ_DM365_TINT7        22
#define IRQ_DM365_SDIOINT0    23
#define IRQ_DM365_MMCINT1    27
#define IRQ_DM365_PWMINT3    28
#define IRQ_DM365_RTCINT    29
#define IRQ_DM365_SDIOINT1    31
#define IRQ_DM365_SPIINT0_0    42
#define IRQ_DM365_SPIINT3_0    43
#define IRQ_DM365_GPIO0        44
#define IRQ_DM365_GPIO1        45
#define IRQ_DM365_GPIO2        46
#define IRQ_DM365_GPIO3        47
#define IRQ_DM365_GPIO4        48
#define IRQ_DM365_GPIO5        49
#define IRQ_DM365_GPIO6        50
#define IRQ_DM365_GPIO7        51
#define IRQ_DM365_EMAC_RXTHRESH    52
#define IRQ_DM365_EMAC_RXPULSE    53
#define IRQ_DM365_EMAC_TXPULSE    54
#define IRQ_DM365_EMAC_MISCPULSE 55
#define IRQ_DM365_GPIO12    56
#define IRQ_DM365_GPIO13    57
#define IRQ_DM365_GPIO14    58
#define IRQ_DM365_GPIO15    59
#define IRQ_DM365_ADCINT    59
#define IRQ_DM365_KEYINT    60
#define IRQ_DM365_TCERRINT2    61
#define IRQ_DM365_TCERRINT3    62
#define IRQ_DM365_EMUINT    63

/*
 * User Peripheral physical base addresses.
 */
#define DM368_BASE_EDMA            0x01c00000  //EDMA
#define DM368_BASE_UART0           0x01c20000  //UART0

#define DM368_BASE_TIMER3          0x01c20800  //TIMER3
#define DM368_BASE_RTO             0x01c20c00  //Real-time out
#define DM368_BASE_I2C             0x01c21000  //I2C
#define DM368_BASE_TIMER0          0x01c21400  //TIMER0
#define DM368_BASE_TIMER1          0x01c21800  //TIMER1
#define DM368_BASE_TIMER2          0x01c21C00  //TIMER2(Watchdog)
#define DM368_BASE_PWM0            0x01c22000  //PWM0
#define DM368_BASE_PWM1            0x01c22400  //PWM1
#define DM368_BASE_PWM2            0x01c22800  //PWM2
#define DM368_BASE_PWM3            0x01c22c00  //PWM3
#define DM368_BASE_SPI4            0x01c23000  //SPI4
#define DM368_BASE_TIMER4          0x01c23800  //TIMER4
#define DM368_BASE_ADCIF           0x01c23c00  //ADCIF

#define DM368_BASE_SYSTEMMODULE    0x01c40000  //System Module Register
#define DM368_BASE_PLL1            0x01c40800  //PLL Controller 1
#define DM368_BASE_PLL2            0x01c40c00  //PLL Controller 2
#define DM368_BASE_PSC             0x01c41000  //Power and Sleep Controller(PSC)

#define DM368_BASE_AINTC           0x01c48000  //ARM Interrupt Control

#define DM368_BASE_USB20           0x01c64000  //USB OTG 2.0 Regs/RAM
#define DM368_BASE_SPI0            0x01c66000  //SPI0
#define DM368_BASE_SPI1            0x01c66800  //SPI1
#define DM368_BASE_GPIO            0x01c67000  //GPIO
#define DM368_BASE_SPI2            0x01c67800  //SPI2
#define DM368_BASE_SPI3            0x01c68000  //SPI3

#define DM368_BASE_PRTCSS          0x01c69000  //PRTCSS Interface Registers
#define DM368_BASE_KEYSCAN         0x01c69400  //KEYSCAN
#define DM368_BASE_HPI             0x01c69800  //HPI

#define DM368_BASE_MMCSD1          0x01d00000  //Multimedia / SD 1
#define DM368_BASE_MCBSP           0x01d02000  //McBSP

#define DM368_BASE_UART1           0x01d06000  //UART1

#define DM368_BASE_EMAC            0x01d07000  //Ethernet MAC(EMAC)
#define DM368_BASE_MDIO            0x01d0b000  //Management Date Input/Output(MDIO)

#define DM368_BASE_MMCSD0          0x01d11000  //Multimedia / SD 0

#define DM365_EMAC_BASE			(0x01D07000)
#define DM365_EMAC_MDIO_BASE		(DM365_EMAC_BASE + 0x4000)
#define DM365_EMAC_CNTRL_OFFSET		(0x0000)
#define DM365_EMAC_CNTRL_MOD_OFFSET	(0x3000)
#define DM365_EMAC_CNTRL_RAM_OFFSET	(0x1000)
#define DM365_EMAC_CNTRL_RAM_SIZE	(0x2000)

/* Miscellania... */
#define VBPR				        (0x20000020)

//System Module Registers
#define SM_PINMUX0                (DM368_BASE_SYSTEMMODULE + 0x0) //Pin Multiplexing Control 0
#define SM_PINMUX1                (DM368_BASE_SYSTEMMODULE + 0x4) //Pin Multiplexing Control 1
#define SM_PINMUX2                (DM368_BASE_SYSTEMMODULE + 0x8) //DSP Boot Address
#define SM_PINMUX3                (DM368_BASE_SYSTEMMODULE + 0xc) //Emulator Suspend Source
#define SM_PINMUX4                (DM368_BASE_SYSTEMMODULE + 0x10) //Boot Status
#define SM_BOOTCFG                (DM368_BASE_SYSTEMMODULE + 0x14) //Device Boot Configuration
#define SM_ARM_INTMUX             (DM368_BASE_SYSTEMMODULE + 0x18) //SmartReflex Status
#define SM_EDMA_EVTMUX            (DM368_BASE_SYSTEMMODULE + 0x1c)

#define SM_HPI_CTL                (DM368_BASE_SYSTEMMODULE + 0x24) //ARM926 Boot Control
#define SM_DEVICE_ID              (DM368_BASE_SYSTEMMODULE + 0x28) //JTADID
#define SM_VDAC_CONFIG            (DM368_BASE_SYSTEMMODULE + 0x2c)

#define SM_TIMER64_CTL            (DM368_BASE_SYSTEMMODULE + 0x30)
#define SM_USB_PHY_CTRL           (DM368_BASE_SYSTEMMODULE + 0x34) //USB Control
#define SM_MISC                   (DM368_BASE_SYSTEMMODULE + 0x38)
#define SM_MSTPRI0                (DM368_BASE_SYSTEMMODULE + 0x3c) //Bus Master Priority Control 0
#define SM_MSTPRI1                (DM368_BASE_SYSTEMMODULE + 0x40) //Bus Master Priority Control 1
#define SM_VPSS_CLK_CTRL          (DM368_BASE_SYSTEMMODULE + 0x44) //Bus Master Priority Control 2
#define SM_PERI_CLKCTL            (DM368_BASE_SYSTEMMODULE + 0x48)
#define SM_DEEPSLEEP              (DM368_BASE_SYSTEMMODULE + 0x4c)

#define SM_DEBOUNCE0              (DM368_BASE_SYSTEMMODULE + 0x54)
#define SM_DEBOUNCE1              (DM368_BASE_SYSTEMMODULE + 0x58)
#define SM_DEBOUNCE2              (DM368_BASE_SYSTEMMODULE + 0x5c)
#define SM_DEBOUNCE3              (DM368_BASE_SYSTEMMODULE + 0x60)
#define SM_DEBOUNCE4              (DM368_BASE_SYSTEMMODULE + 0x64)
#define SM_DEBOUNCE5              (DM368_BASE_SYSTEMMODULE + 0x68)
#define SM_DEBOUNCE6              (DM368_BASE_SYSTEMMODULE + 0x6c)
#define SM_DEBOUNCE7              (DM368_BASE_SYSTEMMODULE + 0x70)
#define SM_VTPIOCR                (DM368_BASE_SYSTEMMODULE + 0x74)
#define SM_PUPDCTL0               (DM368_BASE_SYSTEMMODULE + 0x78)
#define SM_PUPDCTL1               (DM368_BASE_SYSTEMMODULE + 0x7c)
#define SM_HDVICPBT               (DM368_BASE_SYSTEMMODULE + 0x80)
#define SM_PLLC1_CONFIG           (DM368_BASE_SYSTEMMODULE + 0x84)
#define SM_PLLC2_CONFIG           (DM368_BASE_SYSTEMMODULE + 0x88)

/*
//PLL1
#define PLL1_PID               (DM646X_BASE_PLL1 + 0x0)
#define PLL1_RSTYPE            (DM646X_BASE_PLL1 + 0xe4)
#define PLL1_PLLCTL            (DM646X_BASE_PLL1 + 0x100)
#define PLL1_PLLM              (DM646X_BASE_PLL1 + 0x110)
#define PLL1_PLLDIV1           (DM646X_BASE_PLL1 + 0x118)
#define PLL1_PLLDIV2           (DM646X_BASE_PLL1 + 0x11c)
#define PLL1_PLLDIV3           (DM646X_BASE_PLL1 + 0x120)
#define PLL1_BPDIV             (DM646X_BASE_PLL1 + 0x12c)
#define PLL1_PLLCMD            (DM646X_BASE_PLL1 + 0x138)
#define PLL1_PLLSTAT           (DM646X_BASE_PLL1 + 0x13c)
#define PLL1_ALNCTL            (DM646X_BASE_PLL1 + 0x140)
#define PLL1_DCHANGE           (DM646X_BASE_PLL1 + 0x144)
#define PLL1_CKEN              (DM646X_BASE_PLL1 + 0x148)
#define PLL1_CKSTAT            (DM646X_BASE_PLL1 + 0x14c)
#define PLL1_SYSTAT            (DM646X_BASE_PLL1 + 0x150)
#define PLL1_PLLDIV4           (DM646X_BASE_PLL1 + 0x160)
#define PLL1_PLLDIV5           (DM646X_BASE_PLL1 + 0x164)
#define PLL1_PLLDIV6           (DM646X_BASE_PLL1 + 0x168)
#define PLL1_PLLDIV8           (DM646X_BASE_PLL1 + 0x170)
#define PLL1_PLLDIV9           (DM646X_BASE_PLL1 + 0x174)
*/

//AINTC registers
#define AINTC_FIQ0             (DM368_BASE_AINTC + 0x0) //Fast Interrupt Request Status Register 0
#define AINTC_FIQ1             (DM368_BASE_AINTC + 0x4) //Fast Interrupt Request Status Register 1
#define AINTC_IRQ0             (DM368_BASE_AINTC + 0x8) //Interrupt Request Status Register 0
#define AINTC_IRQ1             (DM368_BASE_AINTC + 0xc) //Interrupt Request Status Register 1
#define AINTC_FIQENTRY         (DM368_BASE_AINTC + 0x10) //Fast Interrupt Request Entry Address Register
#define AINTC_IRQENTRY         (DM368_BASE_AINTC + 0x14) //Interrupt Request Entry Address Register
#define AINTC_EINT0            (DM368_BASE_AINTC + 0x18) //Interrupt Enable Register 0
#define AINTC_EINT1            (DM368_BASE_AINTC + 0x1c) //Interrupt Enable Register 1
#define AINTC_INTCTL           (DM368_BASE_AINTC + 0x20) //Interrupt Operation Control Register
#define AINTC_EABASE           (DM368_BASE_AINTC + 0x24) //Interrupt Entry Table Base Address Register

#define AINTC_INTPRI0          (DM368_BASE_AINTC + 0x30) //Interrupt 0-7 Priority Register 0
#define AINTC_INTPRI1          (DM368_BASE_AINTC + 0x34) //Interrupt 8-15 Priority Register 1
#define AINTC_INTPRI2          (DM368_BASE_AINTC + 0x38) //Interrupt 16-23 Priority Register 2
#define AINTC_INTPRI3          (DM368_BASE_AINTC + 0x3c) //Interrupt 24-31 Priority Register 3
#define AINTC_INTPRI4          (DM368_BASE_AINTC + 0x40) //Interrupt 32-39 Priority Register 4
#define AINTC_INTPRI5          (DM368_BASE_AINTC + 0x44) //Interrupt 40-47 Priority Register 5
#define AINTC_INTPRI6          (DM368_BASE_AINTC + 0x48) //Interrupt 48-55 Priority Register 6
#define AINTC_INTPRI7          (DM368_BASE_AINTC + 0x4c) //Interrupt 56-63 Priority Register 7

/* DDR2 Memory */
#define DM368_SDRAM_BASE        0x80000000

struct rt_hw_register
{
    rt_uint32_t r0;
    rt_uint32_t r1;
    rt_uint32_t r2;
    rt_uint32_t r3;
    rt_uint32_t r4;
    rt_uint32_t r5;
    rt_uint32_t r6;
    rt_uint32_t r7;
    rt_uint32_t r8;
    rt_uint32_t r9;
    rt_uint32_t r10;
    rt_uint32_t fp;
    rt_uint32_t ip;
    rt_uint32_t sp;
    rt_uint32_t lr;
    rt_uint32_t pc;
    rt_uint32_t cpsr;
    rt_uint32_t ORIG_r0;
};

#define	REG(addr)	(*(volatile unsigned int *)(addr))
#define REG_P(addr)	((volatile unsigned int *)(addr))

#define readb(a)	(*(volatile rt_uint8_t*)(a))
#define readw(a)	(*(volatile rt_uint16_t*)(a))
#define readl(a)	(*(volatile rt_uint32_t*)(a))

#define writeb(v,a)	(*(volatile rt_uint8_t*)(a) = (v))
#define writew(v,a)	(*(volatile rt_uint16_t*)(a) = (v))
#define writel(v,a)	(*(volatile rt_uint32_t*)(a) = (v))

#endif

